The present invention relates in general to powering integrated circuits, and in particular, to powering DC (xe2x80x9cdirect currentxe2x80x9d) powered integrated circuits within an integrated circuit using an AC (xe2x80x9calternating currentxe2x80x9d) power source.
Providing power to complex integrated circuits in high-speed applications presents a common design problem. With advances in design and manufacture of semiconductor devices, it has become possible to integrate larger amounts of circuitry within an integrated circuit (xe2x80x9cICxe2x80x9d) to enhance overall device functionality. As more circuitry is integrated, there is a corresponding increase in the basic building blocks (i.e., transistors) of the IC. To accommodate the increased number of transistors within an IC, and to provide for faster operation, the transistors are increasingly scaled to smaller dimensions. As transistor size continues to shrink, especially in the field of CMOS technology, power supply voltage levels for CMOS IC devices decrease. Decreasing voltage levels and increasing power demands both cause supply current increases for proper device operation.
Lower supply voltages are required for smaller scaled CMOS devices because as the device dimensions shrink, the gate oxide layer below the gate of a CMOS device is made thinner, which is more susceptible to breakdown when a given gate voltage is applied. Thus, the maximum supply voltage that can be used to power an IC is limited by the breakdown voltage. For example, integrated circuits typically operate at 3.3 Vdc or less, with newer designs approaching supply voltages of 1.0 Vdc.
The power consumed by integrated circuitry increases as a function of both the number of transistors and the switching speed (i.e., clock frequency) associated with a given IC. The power consumed by CMOS ICs is primarily due to charging and discharging circuit node capacitances and can be expressed by the proportion P xcex1 nf, where n is the number of transistors per chip and f is the clock frequency. Therefore, as power consumption increases, the supply current requirements for proper operation also increase.
Although the supply voltages might be reduced in newer designs, a much larger nf factor contributes to the overall increase in consumed power. For example, a 2.5 GHz IC design that once might have called for a supply voltage of 3.0 Vdc and have three million transistors might now call for a supply voltage of 1.0 Vdc and have ten million transistors due to additional functionality added to the IC design. Adding functionality from generation to generation is typical in the IC design industry, especially in the microprocessor business. Because power is proportional to nf, a design that once required 30 watts now requires 100 watts. With the supply voltage going from 3.0 Vdc to 1.0 Vdc, the current requirement go from 10 A to 100 A.
A common approach to supplying large currents to an IC is to use a large number of power pin connections, or bond wires, to the integrated circuitry. FIG. 1 illustrates this with an IC 104 mounted on a carrier 102. IC 104 has a plurality of die pads 110 for receiving power and input/ output (xe2x80x9cI/Oxe2x80x9d) signals from the external environment, with a large number of the die pads reserved for VDD 106 and Ground 108, thus greatly reducing the number of pins available for signal I/O in a pin-limited form factor and unnecessarily increases chip area to accommodate the total number of power pins, making electronic packaging of such a device complicated and expensive.
As shown in FIG. 2, the bond wires (204, 206) which provide external connection (for power or I/O) to an IC 202 can be modeled with parasitic capacitances, parasitic inductances, and parasitic resistances. The above-described parallel power pin approach does reduce the overall parasitic inductance and resistance somewhat, but with large supply current requirements, such as 100 A, even a small overall resistance, such as 1 milliohm, or a small overall inductance, such as 100 fH, on the bonding wires can cause significant voltage drops across the power pin connections. At lower supply voltages, these voltage drops and voltage swings significantly affect device operation and may result in device malfunction.
One measure of effective pin use in the design of semiconductor devices or packaged ICs is the signal-to-power pin ratio (xe2x80x9cpin ratioxe2x80x9d). The pin ratio of a packaged IC is defined as the number of available signal I/O pins divided by the total number of pins. Generally, if more signal I/O pins are available, the more complex functions the device can perform. It is therefore favorable to maximize the pin ratio for a given device, since the cost of using more pins to power the device is the loss of available signal I/O pins as well as reduced device functionality.
The approximate number of power pins required for a device operating at a given supply voltage and consuming a given amount of power can be estimated using Equation 1 where VDD is the supply voltage, in volts, and P is the power required, in watts.                     #        ⁢                  xe2x80x83                ⁢        Power        ⁢                  xe2x80x83                ⁢        pins        ⁢                  xe2x80x83                ⁢        α        ⁢                  xe2x80x83                ⁢                  P                      VDD            2                                              (                  Equation          ⁢                      xe2x80x83                    ⁢          1                )            
As an illustration, a device consuming 30 W at a VDD of 3.0 Vdc only requires about 10 power pins for proper operation. If the device has 400 pins, the pin ratio is quite high (390/400=0.98). However, another 400-pin device operating with a VDD of 1.0 Vdc and at 100 W requires about 300 power pins, resulting in a pin ratio of only 0.25.
Therefore, there is a need in the art for an inventive circuit and method for supplying integrated circuits with power and current requirements while preserving a high pin ratio for semiconductor devices or ICs.
An inventive power converter within an integrated circuit (xe2x80x9cICxe2x80x9d) provides DC power to one or more function circuits where the DC power is derived from an applied external AC power signal conveyed into the IC. In a preferred embodiment, the power converter includes a transformer circuit for receiving and transforming the external AC power signal, and a converter circuit for receiving the transformed AC power signal from the transformer circuit and converting it into a DC power signal. The DC power signal then can be used to power the many circuits within the IC.